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April 5, 2018 2:00 pm - 3:00 pm EDT

Title: Secure Processor for Self-configuring Autonomous Systems

Speaker: Michael Vai, Secure Resilient Systems and Technology Group, MIT Lincoln Laboratory

Location: Northeastern University, 805 Columbus Avenue, 655 Interdisciplinary Science and Engineering Complex (ISEC), Boston, Massachusetts 02120


MIT Lincoln Laboratory (MITLL) has developed a secure processor with strong mission assurance properties specialized for self-configuring autonomous systems. A pertinent example of a self-configuring autonomous system is a swarm of miniaturized drones teamed up to accomplish a mission. Each drone needs to sense its environment, communicate and coordinate with others, and compute its movement with a high degree of confidentiality, integrity, and availability.

Modern processors achieve performance by allowing multiple cores to share a great deal of resources, most notably the memory sub-system (e.g., caches). This sharing permits the cores to cooperate with minimal overhead, but is counter to the security goal of rigidly separating system processes. Virtual separation, implemented with trusted software such as the seL4 separation microkernel, has been used to undo the sharing nature by rigidly separating memory and restricting communication. The security overhead caused by virtual separation may be unacceptable to real-time systems or systems that must process a large amount of data quickly.

We will discuss the development of a heterogeneous secure processor architecture that incorporates a high performance multi-core processor and a lower performance, but easier to verify real-time processor. Minimal, provably correct code will be running on the real-time processor, which is physically separated from the high performance processor provided for more complex software. We will also explain the design methodology used to optimize the processor for self-configuring autonomous systems.

About the Speaker

Dr. Michael Vai joined MIT Lincoln Laboratory in 1999 and is currently Senior Staff in the Secure Resilient Systems and Technology Group. Before coming to this group, he was Assistant Leader of the Embedded and Open Systems Group in the ISR and Tactical Systems Division. At Lincoln Laboratory, he has led the development of several notable real-time systems incorporating very-large-scale integration (VLSI) chips, field-programmable gate arrays (FPGAs), and multicore processors.

Dr. Vai has worked in the area of high-performance embedded computing for more than 20 years. He has worked and published extensively in VLSI, application specific integrated circuits (ASIC), FPGAs, design methodology, and embedded digital systems. He has published more than 100 technical papers and a textbook (VLSI Design, CRC Press, 2001). He is also the co-editor and a contributing author of a reference handbook (High Performance Embedded Computing Handbook, CRC Press, 2008).

Until July 1999, Dr. Vai was on the faculty of the Electrical and Computer Engineering Department, Northeastern University, Boston, Massachusetts. Dr. Vai’s current research interests include secure embedded systems, and particularly those applicable to critical missions.
He is a senior member of IEEE.

Dr. Vai received his MS and PhD degrees from Michigan State University, East Lansing, Michigan, in 1985 and 1987, respectively, all in electrical engineering.



April 5, 2018
2:00 pm - 3:00 pm
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Interdisciplinary Science and Engineering Complex (ISEC)
805 Columbus Avenue
Boston, MA 02120 United States
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(617) 373-8380